image/svg+xmlProduct Development
Graphic Design
User Interface
Powerpoint
User Research
Visual Design
Design Process
Photoshop
CAD
Facebook
Brenda Lane
Brenda Lane
83110 W. Maple Ave., Austin, TX, 47623 |
(750) 555-3161
|
blane@example.com
Experience
Experience
Product Design Internship | Intel, Austin, TX | June 2019 - April 2020
Product Design Internship | Intel, Austin, TX | June 2019 - April 2020
Developed environment to automate generation of control file for Fastscan ATPG using Perl.
Developed and tested Cadence and Mentor Graphics EDA tools with innovative Algorithms for Physical verification and circuit
analysis of semiconductor chips.
Developed C/C++ and Java applications and Perl Scripts for testing complete functionalities of Android and Windows based
Intel Products.
Owned regression reporting and indicators for tracking project model build health status using HTML and CGI.
Improved test program failure data collection efficiency with Perl scripts by collecting all program failures instead of just the
initial failure.
Product Design Internship | Intel, Austin, TX | November 2018 - January 2019
Product Design Internship | Intel, Austin, TX | November 2018 - January 2019
Developed and tested Cadence and Mentor Graphics EDA tools with innovative Algorithms for Physical verification and circuit
analysis of semiconductor chips.
Assisted engineers to use C/Perl to program software.
Conducted user interviews, designed and collected survey data to understand existing sales forecast process.
Implemented a generic JTAG reverse-assembler in Perl for decoding binary test patterns.
Improved test program failure data collection efficiency with Perl scripts by collecting all program failures instead of just the
initial failure.
Design Internship (Part-Time) | Intel, Austin, TX | December 2016 - February 2018
Design Internship (Part-Time) | Intel, Austin, TX | December 2016 - February 2018
Developed and tested Cadence and Mentor Graphics EDA tools with innovative Algorithms for Physical verification and circuit
analysis of semiconductor chips.
Owned regression reporting and indicators for tracking project model build health status using HTML and CGI.
Automated the analysis of IR drop and Power Density using Perl and TCL Scripts.
Coordinated all work with building and facility engineers.
Created original CAD's and techpacks for new AW17 collection.
Education
Education
Bachelor's Degree | 2015 - 2018
Bachelor's Degree | 2015 - 2018
| University of Texas at Austin
| University of Texas at Austin
- Austin, TX
- Austin, TX
Major: Mechanical Engineering
Skills
Skills